1. Field of the Invention
This invention relates to a semiconductor device, more specifically a semiconductor device comprises two elements each of which having capacitor connected in parallel with each other and a method for manufacturing thereof.
2. Description of the Related Art
A programmable logic device (hereinafter referred to as PLD) is known as an large scale integrated circuit(hereinafter referred to as LSI) capable of programming logic functions by the user(s). The PLD is constructed so as to provide a number of logic circuits ready-to-operate on the chip for the LSI, and the logic circuits are connected one another through switches capable of programming. A switching element SW shown in FIG. 6A is considered as one of the switches for the PLD.
The switching element SW is constructed by connecting both of a transistor TR1 for programming and a transistor TR2 for switching with each other as shown in FIG. 6A. The transistor TR1 for programming is a split gate type electrically programmable read only memory (EPROM). Also, floating gates FG of the transistor TR1 for programming and the transistor TR2 for switching are formed continuously in common with each other. Control gates CG of both the transistor TR1 and the transistor TR2 are formed continuously in common with each other.
Either of information ON or OFF is written in the transistor TR1 by applying appropriate voltages to a terminal ES, a terminal ED, the control gate CG and a semiconductor substrate SB. The transistor TR2 connects or disconnects a wiring L1 and a wiring L2 in accordance with the information written in the transistor TR1.
FIG. 6B and FIG. 6C are sectional views showing structures of the transistor TR1 for programming and the transistor Tr2 for switching respectively. In order to write information OFF into the transistor TR1, a voltage which makes the floating gate FG in high potential is applied between the semiconductor substrate SB of the transistor TR1 and floating gate FG1. So that, electrons emitted from a source are attracted and trapped into the floating gate FG. Therefore, writing information is getting easier in proportion to make the floating gate in higher potential compared with the potential of the semiconductor substrate SB.
FIG. 7 shows an equivalent circuit of the transistor TR1 and the transistor TR2 in assumption of the switching element SW as connection of a plurality of capacitor. A voltage VL generated between the floating gate FG and the semiconductor substrate SB is calculated by an equation shown in FIG. 7, in case of a capacitance accumulated between the control gate CG and the floating gate FG is shown as C1U, C2U, a capacitance accumulated between the control gate CG and the semiconductor substrate SB is shown as C1L, C2L, and a voltage generated between the control gate CG and the semiconductor substrate SB is shown as V.
In other words, both the capacitance C1U and C2U should be increased in order to make the voltage VL in large value. To do that, it is preferable to use an ONO layer (a layer having triple layered structure such as silicon oxide layer-silicon nitride layer-silicon oxide layer) having a high charge-storage characteristic as an inter-layer film SM located between the control gate CG and the floating gate FG.
Further, it is necessary to make the capacitance accumulated between the control gate and the floating gate FG of the transistor Tr1 in a fixed value in order to decrease variation of the voltage VL. So that, the control gate CG is formed so as to cover both the floating gate and the inter-layer film SM as shown in FIG. 6B. The capacitance C1U does not receive adverse effect even when the control gate CG is mis-aligned to the floating gate FG.
On the other hand, the place where the electrons are attracted to the floating gate FG is vicinity of the drain D, because movement of the electrons is accelerated sufficiently at vicinity of the drain D. So that, the drain D should be located right beside the floating gate FG.
In order to satisfy the requirements stated in the above, the drain D is formed by carrying out ion implantation of arsenic with self-alignment method by utilizing both the floating gate and the inter-layer film SM as a mask after forming the floating gate and the inter-layer film SM made of the ONO layer as shown in FIG. 8A. Thereafter, the control gate CG is formed so as to cover both the floating gate FG and the inter-layer film SM (see FIG. 8B, FIG. 8C). Thus, the switching element SW is completed.
However, the method for manufacturing the switching element described in the above has following disadvantages. As shown in FIG. 8A, upper surface of the ONO layer composing the inter-layer film SM which consisting a part of the mask is damaged during the ion implantation of arsenic with self-alignment method by utilizing both the floating gate and the inter-layer film SM as the mask. The damages lead degradation of charge-storage characteristic of the ONO layer because thickness of the ONO layer is very thin. So that, there is high probability to cause short-circuit between the control gate and the floating gate FG of the transistor TR1.